1. Field of the Invention
The present invention relates to semiconductor memory devices, and more specifically to circuitry for correcting a memory device in which some cells have low remanence.
2. Description of Related Art
An important feature of the performance of a dynamic random access memory device (DRAM) is the refreshment time, which is the maximum time that can pass between refreshments of the memory contents without degrading the stored information. A memory cell having a long refreshment time is said to have a high remanence. In spite of the progress made in manufacturing reliability, a memory device still can have manufacturing defects that make it inoperative (e.g., due to the introduction of an impurity during manufacturing). When such a defect appears in the memory array circuitry, which is relatively frequent due to the predominate surface of the array with respect to the memory surface, due to the great regularity of the structure of a memory array it is possible to easily replace the array area containing the defect with an identical spare area provided for this purpose.
FIG. 1 shows a conventional 1-megabit DRAM. The array 10 of the DRAM is organized into 1024 columns of 1024rows, with the columns being gathered in eight sets D0 to D7 of 128 columns to define 1024.times.128 8-bit words. Additionally, spare columns 12 of 1024 rows are located close to the array columns. A row decoder 14 selects a row from among the 1024 in the array and spare columns based on a row address ROW. A control circuit 16 receives a column address COL and selects the group of eight columns corresponding to this address. The control circuit also includes a non-volatile memory 18 that can be programmed so that a spare column systematically corresponds to a specific column address, instead of the array column that normally corresponds to this address. Thus, once the non-volatile memory has been programmed, it is possible to systematically replace some array columns considered to be defective with the spare columns, transparently for the user, for the write and read operations in the memory.
To determine whether a column is defective (i.e., whether it contains a defective cell), before being sold the memory is tested by a machine that performs several writings and readings over all array cells. The cell defects that are searched are redhibitory defects such as those that block the value provided by a memory cell or neighboring memory cells. The successive test writings and readings follow a predetermined sequence to locate with certainty all defective cells in the array. When the testing locates a defective cell, the non-volatile memory of the control circuit is programmed to replace the defective column with a spare column.
The non-volatile memory of the circuit is known as a "fuse box" and can be accessed from the circuit surface, with the memory programming being performed by fusing a combination of fuses using a laser beam. A relatively large number of fuses typically must be fused to correct a defect, and thus such laser programming does not have very high reliability. As a result, it is generally chosen not to correct more than about ten defects per array. If an array has a higher number of defects, the tester will reject the memory device as irreparable. This restricted number of repairs limits the necessary number of spare columns, and thus limits the surface and cost increase of the DRAM. As an example, one spare column is typically provided for 64 or 128 functional array columns.
In addition to the type of redhibitory defect described above, there is a type of defect known as a memory point remanence defect that alters the operation of a DRAM. A remanence defect, which is caused by physical characteristics (e.g., crystal dislocations or impurities in the material), results in an abnormally fast loss of information in a memory point. The occurrence of such defects forces the user to refresh the information stored in the DRAM more often than in the absence of such defects. In practice, a DRAM having such defects must be sold with lower guaranteed performance (i.e., a shorter refresh interval), and thus with lower functionality and a lower price.
Further, this type of defect generally appears in a large number of cells. As an example, in DRAM arrays produced using conventional manufacturing methods, approximately 10 to 100 cells per million have a low remanence. Because these low remanence cells are distributed randomly, a very large number of columns can be affected by having at least one cell with a defect. To repair such a large number of cells through conventional memory array repair techniques (such as described above with respect to FIG. 1) would require increasing the surface of the array by at least 30% in order to include the necessary number of spare columns.
Additionally, the programming of the non-volatile memory of the decoder would require the laser fusing of a large number of fuses, and the poor reliability of such an operation would adversely affect the quality of the repairs. For example, assuming that the probability of properly fusing a fuse with a laser is 99.5% and that 20 fuses have to be fused to correct an address, the probability of properly performing the correction of 50 addresses is ((0.995).sup.20).sup.50 .apprxeq.0.006, which is extremely low. Further, the spare columns themselves can also include defects (statistically, 30% of the spare columns). Thus, it is not possible to correct such defects unless very large and costly additional circuitry is provided.